aionescu cmc dec06

Information about aionescu cmc dec06

Published on October 30, 2007

Author: Belly

Source: authorstream.com

Content

Slide1:  Y. Chauhan, F. Krummenacher and A. M. Ionescu Ecole Polytechnique Fédérale de Lausanne (EPFL), Switzerland Progress and update in HV-EKV Model http://legwwww.epfl.ch Outline:  Outline HV-EKV: status and people short comment on evaluation feedback New validations: model validation on SOI-LDMOS (AMIS) demonstration of quasi-saturation modeling on VDMOS (AMIS) NEW – Modeling of Lateral Non-uniform doping in HVMOS (see IEDM’06 paper) HV-EKV (1):  HV-EKV (1) EKV • Simple, physically based parameters • Less parameters than BSIM HVEKV: EKV low voltage + Rdrift + charge (Vk) Slide4:  HV-EKV (2): scalable drift resistance HV: who @ EPFL?:  HV: who @ EPFL? Yogesh Chauhan (100%) Francois Krummenacher (EKV team, 25%) Costin Anghel (now with CEA, France) Adrian M. Ionescu, prof. (~10%) Michel Declercq, prof. (~10%) High Voltage MOS modeling: a strategic field but not our mainstream research à reorganization needed if HV-EKV adopted by CMC Electronics Laboratory (50 people, 4 profs, 24 PhDs) HV-EKV –status and feedback:  HV-EKV –status and feedback Status: corrected code released to CMC and evaluations in progress Feedback: simplicity, ease of extr, doc: + Accuracy problem in quasi-saturation: - Accuracy with temperature: - Relatively slow because of Verilog A Compared with sub-circuit models: evaluators agree it’s a compact model! In fact needs appropriate tunning Problem with quasi-saturation?:  Problem with quasi-saturation? Tune avsat: quasi-sat for LDMOS and VDMOS! ? ! Model Validation on SOI-LDMOS (1):  Model Validation on SOI-LDMOS (1) Very accurate on both ID-VG and gm-VG @ low VD Model Validation on SOI-LDMOS (2):  Model Validation on SOI-LDMOS (2) Good accuracy on both ID-VG and gm-VG @ high VD Model Validation on SOI-LDMOS (3):  Model Validation on SOI-LDMOS (3) quasi-saturation very well modeled good/acceptable accuracy on gds-VD Quasi-Saturation Modeling on VDMOS:  Quasi-Saturation Modeling on VDMOS in contrast with some criticism the model is able to accurately describe the quasi-saturation region of VDMOS New model extension:  New model extension Model of LAteral Non-Uniform Doping in the intrinsic MOSFET (new EKV-like model for the low voltage transistor) Verilog A code not yet available Evaluated with Matlab code on both numerical simulations and experimental data Reported in IEDM 2006 Why LAMOS modeling?:  Why LAMOS modeling? Modeling of Lateral Non-uniform doping in HV-MOSFET:  Modeling of Lateral Non-uniform doping in HV-MOSFET Assume Total Inversion Charge Density Drain Current Nonlinear ODE Not explicit Model Validation on 50V VDMOS:  Model Validation on 50V VDMOS Transfer Characteristics (ID-VG) Weak inversion to Strong inversion transition Subthreshold slope correctly matched Good accuracy gm-VG for VD=0.1-0.5V:  gm-VG for VD=0.1-0.5V Subthreshold slope correctly matched Descending slope – drift resistance Output Characteristics:  Output Characteristics Linear region correctly modeled by drift resistance. Self Heating Effect Peaks on gds Self-Heating Impact-Ionization Gate-to-Drain Capacitance CGD vs VG :  Gate-to-Drain Capacitance CGD vs VG Slope & Peaks – effect of lateral non-uniform doping Sharp decrease – effect of drift region (good modeling of drift region or VK must) CGS+CGB vs VG :  CGS+CGB vs VG Peaks – effect of lateral non-uniform doping Sharp decrease and shift of peaks – effect of drift region CGG vs VG :  CGG vs VG Peaks and shift of peaks – little contribution from lateral non-uniform doping and greater contribution from drift region Conclusion:  Conclusion General HV-MOS Model including lateral non-uniform doping (code will be available in March 2007) Complex capacitance behavior of high voltage MOS was explained using numerical device simulations A new model for lateral non-uniformly doped devices was presented Self-Heating effect included Very good performance in DC and transient operations Model validated on industrial devices – VDMOS and LDMOS Peaks and shift of peaks in capacitances with bias correctly modeled Slide22:  Christian Maier, Heinisch Holger Robert Bosch, Germany Andre Baguenier Desormeaux Cadence Design Systems, France B. Desoete AMI Semiconductor, Belgium J.-M. Sallesse, A.S. Roy EPFL, Switzerland Acknowledgements Funded by European Commission project “ROBUSPIC” Website- http://www-g.eng.cam.ac.uk/robuspic/

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