bruschi

Information about bruschi

Published on October 8, 2007

Author: Pumbaa

Source: authorstream.com

Content

A. Bertin, M. Bruschi, S. De Castro, L. Fabbri, P. Faccioli, B. Giacobbe, F. Grimaldi, I. Massa, M. Piccinini, M. Poli, C. Sbarra, N. Semprini-Cesari, R. Spighi, M. Villa, A. Vitale, A. Zoccoli:  A. Bertin, M. Bruschi, S. De Castro, L. Fabbri, P. Faccioli, B. Giacobbe, F. Grimaldi, I. Massa, M. Piccinini, M. Poli, C. Sbarra, N. Semprini-Cesari, R. Spighi, M. Villa, A. Vitale, A. Zoccoli La partecipazione del gruppo di Bologna (luminometro) alle attivita’ di ATLAS Slide2:  Contenuto Le attività del gruppo di Bologna in ATLAS: Test delle schede di elettronica del LVL1 per le camere a Muoni Luminometro (LUCID): elettronica di lettura e di trigger + simulazioni Presentazione del progetto L’elettronica di LUCID e stime (preliminari) dei costi Altri interessi del gruppo: Partecipazione alla fisica & trigger di alto livello: fisica di alto Pt e diffrattiva Partecipazione al computing Attività sul LVL1 a Bologna:  Attività sul LVL1 a Bologna Il test delle schede di elettronica del LVL1 (prodotte da Roma1) per le camere a Muoni, verrà effettuato a Bologna. Inizio: Settembre 2005. Test di: ~800 Pad-OR ~800 mother boards con test JTAG e ELMB Rate di test richiesto: 7 board/day Tempo previsto per il test del sistema: >6 mesi Attività sul LVL1 a Bologna - II:  Attività sul LVL1 a Bologna - II Prima riunione e trasporto del materiale il 7 Settembre. La scorsa settimana testate le prime 20 schede OR Le rimanenti schede OR (~800) in viaggio verso Bologna. Inizio lavoro sistematico sull’intero sistema (OR+mother) ad inizio Ottobre. 3 persone dedicate full-time al lavoro (2 su fondi universitari) + altre a rotazione.  Schedula dettagliata del test a Ottobre. Slide5:  ATLAS -LUMINOSITY Importance of Luminosity measurements: Cross sections for “Standard “ processes t-tbar production W/Z production …… Theoretically known to better than 10% ……will improve in the future New physics manifesting in deviation of  x BR relative the Standard Model predictions Important precision measurements Higgs production  x BR tan measurement for MSSM Higgs …… Slide6:  Higgs coupling tan measurement Some examples Systematic error dominated by luminosity (ATLAS Physics TDR ) ATLAS –Luminosity (cont.) Slide7:  ATLAS Luminosity Measurement Program Relative luminosity a DEDICATED luminosity monitor is needed  LUCID LUCID will provide the luminosity per BX as well Absolute luminosity Goal: measure L with ≲ 2-3% accuracy How: LHC Machine parameters Use ZDC in heavy ion runs to understand machine parameters rates of well-calculable processes:e.g. QED, QCD optical theorem: forward elastic rate + total inelastic rate: needs ~full |η| coverage-ATLAS coverage limited Use tot measured by others (TOTEM) Combine machine luminosity with optical theorem luminosity from Coulomb Scattering  Roman Pots ATLAS pursuing all options  Roman Pots Motivations for LUCID:  Motivations for LUCID Requirements: A very radiation hard detector to be used as luminosity monitor Good time resolution to resolve individual beam crossings Insensitive to soft background particles Pointing capability A large dynamic range and no saturation at the highest luminosity A simple, robust and cheap construction Solution: LUCID: LUminosity measurement using a Cherenkov Integrating Detector - The design is based on the Cherenkov Luminosity Counter (CLC) that is operating successfully at CDF. - Gas filled tubes around the beampipe act as a Cherenkov detector and detects particles from the I.P. that are above the Cherenkov threshold (2.7 GeV for pions and 9 MeV for electrons) Basics of the detector:  Basics of the detector 2 detectors x 200 Al tubes filled with C4F10 or Isobutane at atmospheric pressure Winston cones at the end of the tubes focus the Cherenkov light onto quartz fibres Beampipe The fibre read-out:  The fibre read-out General Considerations-I:  General Considerations-I The purpose of this talk is to describe a possible baseline for the design of the ATLAS luminometer (LUCID) readout electronics and trigger scheme. Our aim (since last June) is to achieve, as soon as possible, the following points: Define the general scheme of the electronics Tune, by MC simulation and test beam, the final design parameters Provide a cost estimate per readout channel and time schedule for the realization of the electronics Start as soon as possible with the design in order to be ready in 2007 General Considerations-II:  General Considerations-II Main Goals of the LUCID electronics: For each triggered event (ROD level): Number of tracks Tracks time of arrival Monitor level Number of tracks per bunch Tracks time of arrival per bunch Trigger Level Provide a fast trigger on “properly” filled bunch or on-time events Provide a RAP-GAP vetoing for forward physics Strategy: exploit available FED solutions where possible Slide13:  High Occupancy ~30% (at max. luminosity) Max. 3 tracks/tube (at max. luminosity) The amount of information to be handled @L1 can be encoded in 18 bit MAPMT and FE are in a low level radiation area for electronics (5 Gray/year) Known Facts Slide15:  System Architecture FRONT END (FEPCB) Similar to Roman Pot FE: OPERA/MAROC chip Input: MAPMT Output: DIGITIZED INFORMATION on LVDS Links (~0.5 Gb/s) 22x2 M A P M T L V D S L I N K S VME BUS: TTCvi, CTRL sign.,etc ROS ROD ROD ROD ROD T R I G G. C A R D HV FE CONTROL PC THE OPERA/MAROC CHIP BLOCK FUNCTIONALITY DIAGRAM:  Photomultiplicator Photons Preamp. Bipolar Fast Shaper Unipolar Fast Shaper Trigger Gain correction 4 discriminator thresholds MUX_OUT 1 Multiplexed current output (for channel monitor) TRIG_OUT 63 Trigger outputs x 2 bit/output/BX on 9 LVDS TX 6 Bits (2n-4, n=0..5) 4 x 10 bits DACs SUM_OUT 9 Signal current outputs (sum over 7 out) THE OPERA/MAROC CHIP BLOCK FUNCTIONALITY DIAGRAM 9 1 63 Modifications for Lucid in blue text Slide17:  OPERA/MAROC chip : LAYOUT Technology: SiGe 0.35 m Submitted mid-June, expected mid September Chip area : 12 mm2 (3.5mm *3.9mm) 64 channels, 3.5V power supply Power consumption : 350 mW 228 pins A lot of flexibility: Gain adjustment per channel (6 bits) 4 thresholds Multiplexed currentmeasurement 1 tube  7 readout channel 1 mapmt  9 tubes Output for LUCID: 9 current (sum over 7 channels) 1 current (multiplexed for channel control) 63 x 2 bit (80 MHz clock, for trigger) Slide18:  Single Tube Readout Unit (7 channels) to the trigger unit Fan Out TDC Window Programmable Comparator GI + ADC Multiplicity per Tube LUT 8 8 2 1 3 TUBE LUT (260 kB) 2 2 2 2 2 2 3 #1 #7 LVDS S/P 1/9 data from the MAROC CHIP MAROC CHIP SUM_OUT STRU Discr. (Prog. Thr +NR) TDC START STOP ADC GATE RAW DATA TO READOUT per STRU ~ 5-6 Bytes/BX 1 2 18 Slide19:  stru 1 stru 2 stru 20 SUM_OUT 1_1 SUM_OUT 1_2 SUM_OUT 2_10 LVDS 1_1 LVDS 1_2 LVDS 2_9 LVDS S/P LVDS S/P 3 3 3 LVDS 1_1 (to trig. unit) LVDS 1_2 (to trig. unit) LVDS 2_1 (to trig. unit) LVDS 2_2 (to trig. unit) stru 2 TTCRQ i.f. opt. lnk from TTCIX VME P1 VME I.F DPRAM DPRAM DPRAM CTRL LOGIC 6 Bytes 6 Bytes 6 Bytes EVENT BUFFER s-LINK to ROS from CTRL LOGIC from CTRL LOGIC 160 MB/s s-LINK Busy LUCID ROD BOARD (22 units + spares) – VME 9U Analog_In 1 Analog_In 2 Analog_In 20 LVDS_In 1 LVDS_In 2 LVDS_In 18 ~200 Bytes/ev Slide20:  Signal Buffer TTCRQ i.f. opt. lnk from TTCIX VME P1 VME I.F CTRL LOGIC s-LINK to ROS 160 MB/s s-LINK Busy LUCID TRIGGER BOARD (1 unit + spares) – VME 9U D e t e c t o r 1 D e t e c t o r 2 LVDS 1_1 LVDS 1_2 LVDS 22_1 LVDS 22_2 1 2 43 44 LVDS 23_1 LVDS 23_2 LVDS 44_1 LVDS 44_2 1 2 43 44 Signal Buffer FPGA based TRIGGER PROCESSING UNIT 44 ser. Inp 594 bit/BX 44 ser. Inp 594 bit/BX to the L0 trigger ~200 Bytes/ev Algorithm: MC simulations are needed Description of the main building blocks of the readout electronics:  Description of the main building blocks of the readout electronics OPERA MAROC CHIP Adapted to LUCID needs from the RP design (ATLAS Orsay group) Gated Integrator + ADC 8 bit for the total sum should be enough Contacts have been taken with the LHCb preshower group (Clermont) for adapting their GI+ADC solution TDC 25 ns full range; 300 ps MAPMT resolution  7-8 bit CERN HPTDC will be used (32 channel at 2MHz  2 channels at 32 MHz, but still convenient) LOGIC Mainly Based on LUT (but still to be optimized) IMPLEMENTED on FPGAs Flexible and robust ENGINEERING Integration has to be studied but standard VME 9U will be probably preferred First Costs Estimate:  First Costs Estimate TOTAL Tentative Time Schedule:  Tentative Time Schedule (full production) (full production) (full production) (3 units) (25 units) (2 units) Time Profile:  Time Profile Goals of the project Detector ready beginning 2007 FED and ROD ready in 2007 in useful time before the start of LHC operation Trigger Board before the end of 2007 Funding Profile according to these goals: Next Steps: System Optimization (Test Beam & MC):  Next Steps: System Optimization (Test Beam & MC) Study the best solution for the tube readout (gas pressure, number and type of fibers per tube, MAPMT type)  Test Beam at DESY October Main goals of the Test beam (1/10-14/11): Photon generation, transfer and losses Generation, processing and transmission of electrical signals Baseline Readout Device: MAPMT H 7546 (64 ch-UV glass win.) MC Study to refine design parameter (TDC & ADC resolution), occupancy (# of channels), trigger algorithm TEST BEAM: the MAPMT-FIBERS connection:  TEST BEAM: the MAPMT-FIBERS connection Slide27:  Richieste finanziarie 2006 (variazioni rispetto ai moduli in colore violetto) Richieste finanziarie 2006: M.I. : 21 k€ metabolismo M.E. : 142.5 k€ metabolismo + test beam + C&I Consumo: 21 k€ metabolismo (+5 k€ per l`attivita` sul LVL1) Inventario: 17.5 k€ farm di computing per analisi (Tier 3 like) in comune con il gruppo BO-RPC (responsabile per I 2 gruppi: F. Semeria) Costruzione apparati: 270k€ (<350k€ ) per elettronica LUCID Comprendenti PM, Cavi, crates etc. Trasporti: 3 k€  (per l`attivita` sul LVL1) Conclusions:  Conclusions The Bologna Group activities in ATLAS are started I many different areas. The group will test the LVL1 boards (~830 Pad-OR and mother boards) in Bologna. The setting-up is started. The systematic work will begin in October. The group is involved in the LUCID detector (lumi monitor). Main activities are concerning: MC simulations Electronic design BACKUP:  BACKUP Conclusions - II:  Conclusions - II We are developing, based on the present knowledge of the detector, a baseline design of the LUCID electronics We consider this baseline being in a quite advanced stage and capable to fulfill the detector requirements (more: with the TDC options LUCID become an IMPORTANT DETECTOR for the ATLAS DATA TAKING) Forthcoming test beam and MC simulation will be valuable inputs to improve (in case, simplifying) the design We have already solutions at hand for critical devices (front-end chip, G.I.,ADC, TDC) that make us confident for a start of data taking together with LHC More infos:  More infos - Groups involved in LUCID: University of Alberta, University & INFN Bologna, CERN, University of Lund, University of Montreal, Max Planck Institute, University of Manchester (?), SACLAY Italy would represent ~50% of the group - Total cost of the project for INFN : ~ 400 k€ Would represent ~50% of the total cost General Considerations-III:  General Considerations-III For the description of the readout electronics I will refer essentially to the baseline of the detector described in the LOI Detector: formed by two parts each one consisting of 200 Cherenkov counters (tubes) 5 layers/section x 40 tubes/layer x 7 fibers/tube x 2 sections = 2800 fibers Signal: Prompt particles coming from the IP (primaries) will traverse the full length of the counter and generate a large amplitude signal in the photo-detector Background I: Particles originating from secondary interaction of prompt particles in the detector material and beam-pipe (secondaries) are softer and will traverse the counters at larger angles (multiple reflections), with shorter path lengths Background I significantly smaller than signal Background II: Particles crossing the readout fibers will produce light only on the crossed fibers  Background II will have different pattern of hit fibers wrt signal Signal amplitude measurement:  Signal amplitude measurement CLC have the important feature to guarantee a proportionality between the number of primary particles traversing a single tube and the resulting signal amplitude. These detectors response is not subjected to Landau fluctuations (present in scintillators) and the counter’s amplitude distribution will show distinct peaks for the different particle multiplicities hitting the counters.  LUCID, with an appropriate readout and trigger system can provide the Total Tracks multiplicity per BX Signal time-of-arrival measurement:  Signal time-of-arrival measurement A “precise” measurement of the arrival time of a track in the LUCID detector will help to: Reject off - BX background sources (part of beam gas interactions, satellites BX, interactions originating off-IP) Provide a detailed BX structure monitor Guarantee the selection of events in time with the readout electronics of all the ATLAS detector  IMPORTANT TOOL FOR THE WHOLE ATLAS DATA TAKING Hit fibers pattern Important to reject Background (essentially of type II) Location of the detector:  Location of the detector Situation when the forward shielding is removed:

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