Chapter6

Information about Chapter6

Published on January 1, 2008

Author: Gavril

Source: authorstream.com

Content

Peripheral Component Interconnect (PCI):  Peripheral Component Interconnect (PCI) PCI based System:  PCI based System PCI Address Space:  PCI Address Space Peripheral devices have their own memory space PCI :PCI I/O, PCI Memory (device driver) PCI Configuration Space ( initialization) ISA I/O, ISA Memory (device driver) PCI Configuration Header:  PCI Configuration Header Allow system to identify and control the device Every PCI slot has it’s PCI Configuration Header in an offset that is related to it’s slot on the board PCI Configuration Header:  PCI Configuration Header PCI Configuration Header:  PCI Configuration Header Vender Identification Device Identification Status Command Class Code SCSI : 0x0100 Base Address Register Interrupt Pin (PCI device interrupt pin) Interrupt Line (route interrupt to proper handler) PCI I/O and PCI Memory Address:  PCI I/O and PCI Memory Address PCI configuration code turns on using Command field Linux drivers read/write PCI I/O and PCI memory addresses PCI-ISA Bridges:  PCI-ISA Bridges The PCI specification copes with this by reserving the lower regions of the PCI I/O and PCI Memory address spaces for use by the ISA peripherals in the system and using a single PCI-ISA bridge to translate any PCI memory accesses to those regions into ISA accesses PCI-PCI Bridges:  PCI-PCI Bridges PCI-PCI bridges only pass a subset of PCI I/O and PCI memory read and write requests downstream Linux device drivers only access PCI I/O and PCI Memory space via these windows PCI-PCI Bridges: PCI I/O and PCI Memory Windows:  PCI-PCI Bridges: PCI I/O and PCI Memory Windows A cycle is just an address as it appears on the PCI bus Type 0 Configuration Cycle Bits 31:11 of the Type 0 configuration cycles are treated as the device select field PCI-PCI Bridges: PCI I/O and PCI Memory Windows:  PCI-PCI Bridges: PCI I/O and PCI Memory Windows Type 1 PCI Configuration cycles contain a PCI bus number and this type of configuration cycle is ignored by all PCI devices except the PCI-PCI bridges Type 1 PCI Configuration Cycles:  Type 1 PCI Configuration Cycles The primary bus interface being the one nearest the CPU Secondary bus interface being the one furthest away Subordinate bus number is the highest numbered PCI bus downstream of the PCI-PCI bridge Type 1 PCI Configuration Cycles:  Type 1 PCI Configuration Cycles Ignore it if the bus number specified is not in between the bridge's secondary bus number and subordinate bus number (inclusive), Convert it to a Type 0 configuration command if the bus number specified matches the secondary bus number of the bridge, Pass it onto the secondary bus interface unchanged if the bus number specified is greater than the secondary bus number and less than or equal to the subordinate bus number. Type 1 PCI Configuration Cycles:  Type 1 PCI Configuration Cycles Pass it onto the secondary bus interface unchanged if the bus number specified is greater than the secondary bus number and less than or equal to the subordinate bus number. Linux PCI Initialization:  Linux PCI Initialization PCI device driver This pseudo-device driver builds a linked list of data structures describing the topology of the system PCI BIOS PCI Fixup system specific fixed up code The Linux Kernel PCI Data Structures:  The Linux Kernel PCI Data Structures The PCI Device Driver:  The PCI Device Driver A function of the operating system called at system initialization time Scan all of the PCI buses in the system looking for all PCI devices in the system (including PCI-PCI bridge devices) Configuring PCI-PCI Bridges - Assigning PCI Bus Number Assigning PCI Bus Number (1):  Assigning PCI Bus Number (1) Assigning PCI Bus Number (2):  Assigning PCI Bus Number (2) Assigning PCI Bus Number (3):  Assigning PCI Bus Number (3) Assigning PCI Bus Number (4):  Assigning PCI Bus Number (4) PCI Fixup:  PCI Fixup For non-Intel based system allocates it space in PCI I/O and/or PCI Memory moves on the global PCI I/O and Memory bases by the appropriate amounts, enables the device's use of PCI I/O and PCI Memory,

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