VLSI Symp 2 10 2007

Information about VLSI Symp 2 10 2007

Published on October 9, 2007

Author: Haggrid

Source: authorstream.com

Content

2007 Symposia on VLSI Circuits and Technology:  2007 Symposia on VLSI Circuits and Technology ADCOM Meetings Committee February 10, 2007 Review of 2006 Symposia:  Review of 2006 Symposia Circuits Symposium – Excellent Attendance Registration = 412 (vs. 401 in 2003) Circuits Short Course = 110 (vs. 96 in 2004) Paper submissions – record high submissions 113 accepted of 414 submissions = 27% accept rate vs. 108 of 329 in 2004 Technology Symposium – Record Attendance for US Registration = 641 (vs. 636 in 2004) Technology Short Course = 259 (vs. 252 in 2004) Paper submissions 92 papers accepted of 295 submissions = 31% accept rate vs. 96 of 304 accepted in 2004 All Electronic Presentations Produced CD ROM Media Kit 2007 VLSI Symposium:  2007 VLSI Symposium 2007 Symposium hosted by JFE Rhiga Royal Hotel – Kyoto, Japan – June 14-16 Paper pre-selection meeting – Wednesday Final selection meeting in Japan 2/22 Continued upswing in papers 342 vs 259 in 2005 Changes for 2007/2008:  Changes for 2007/2008 Investigating 2 day overlap with Tech. in 2008? Digital Paper Solicitation Encourage non-traditional papers by example Interactions with systems or different technology layers Publish rating criteria for digital papers to the TPC Solicited papers rated same as regular papers TPC chairs will track solicited papers during selection New publicity chair: Sreedhar Natarajan Press conferences in China, India, Japan, Korea, US Call-for-Paper revised Broader call for digital submissions Emphasis on system wireless, not to compete with RFIC Clearer pre-pub policy Short Courses Advanced Topics on Multi-Standard Wireless Transceiver RFIC Designs Design for Variability in Logic, Memory and Microprocessors Rump Sessions → includes 1 session of invited talks 1 circuit rump (memory, digital, or analog - Thursday) 1 evening speakers (4 talks on special topic - Thursday) Joint rump (Wednesday) Circuits Submissions & Acceptance:  Circuits Submissions & Acceptance 2006 Registration & Short Course:  2006 Registration & Short Course Registration History:  Registration History ~25% joint registration ~$75 joint registration discount Financials:  Financials ~$18K surplus for Circuits Symposia in 2006 vs. $11K in ’04 2007 Symposia hosted in Kyoto – Rhiga Royal Hotel Budgeting for 2008 Registration 400 vs. 412 in 2006 Short Course 100 vs. 110 in 2006 Backup:  Backup Short Course / Workshop (June 13th):  Short Course / Workshop (June 13th) Digital Short Course Title: “Design for Variability in Logic, Memory and uProcessors” Organizers: NAE Vivek De (Intel) JFE M. Mizuno-san (NEC) Analog Workshop Title: “Adv. Topics on RFIC Design for Wireless Networks” Organizers: NAE: Foster Dai (Auburn Univ.) JFE: Hiroki Ishikuro (Keio Univ.) JFE Invited Plenary Speakers:  JFE Invited Plenary Speakers “Beyond 3G Radio” Speaker: Koji Chiba - NTT Docomo “Flexible Electronics” Speaker: Prof. Takao Someya - University of Tokyo “Limits of Power Consumption in Analog Circuits” Speaker: Prof. Hae-Seung Lee - Massachusetts Institute of Technology “Microprocessors enabling Future Game Consoles” Speaker: Jeff Brown - IBM 2007 NAE TPC (New members in blue):  2007 NAE TPC (New members in blue) Rump Sessions: Topics and Organizers:  Rump Sessions: Topics and Organizers Circuit Symposium Overall Organizers NAE: C.K. Ken Yang, UCLA JFE: Kazutoshi Kobayashi, Kyoto University Analog: June 14th (Thu.) Title: “Analog scaling and SoC integration” (Special Talks) NAE: Bram Nauta, University of Twente JFE: Akira Matsuzawa, Tokyo Institute of Technology Digital/Memory: June 14th (Thu.) Title: “CMOS scaling: where will economics set the "end of the line?” NAE: Ken Shepard, Columbia University JFE: Masaki Hirata, NEC Electronics Joint: June 13th (Wed.) Title: “Is compact modeling measuring up to the challenge of the DFM era?” Circuits NAE: Azeez Bhavnagarwala, IBM Circuits JFE: Shigetaka Kumashiro, NEC Electronics Technology NAE: Rafael Rios (Intel) Technology JFE: Shinji Odanaka Digital Short Course (June 13th):  Digital Short Course (June 13th) Title: Design for Variability in Logic, Memory and Microprocessors Organizers: Masayuki Mizuno (NEC), Vivek De (Intel) Abstract: Device variability is having large impacts on circuit designs for both logic and memory. Lithography and manufacturing trends, voltage headroom scaling, and increasingly non-ideal transistors and wirings continue to degrade timing predictability, various design margins, power and performance. This short course will introduce design techniques for managing variability. Program schedule: 8:10 to 8:15am Introduction 8:15 to 9:25am Basics of variations Sani Nassif, IBM 9:25 to 10:35am Variation-aware methodologies & tools Andrzej Strojwas, PDF Solutions 10:35 to 10:50am Coffee break 10:50 to 12:00pm Low power ASIC design Kenichi Osada, Hitachi 12:00 to 1:30pm Lunch 1:30 to 2:40pm Microprocessor design James Tschanz, Intel 2:40 to 2:55pm Coffee break 2:55 to 4:05pm Variation-tolerant SRAM design techniques Mike Clinton, TI 4:05 to 5:15pm DRAM design TBD, Elpida 5:15pm Conclusion Wireless Workshop (June 13th):  Wireless Workshop (June 13th) Title: Advanced Topics on Multi-Standard Wireless Transceiver RFIC Designs Organizers: Hiroki Ishikuro (Keio University), Foster Dai (Auburn University) Abstract: With WLAN, WiMAX, DVB and cellural standards operating in very different frequency bands, market leading wireless solutions have to offer multi-mode interoperability with transparent worldwide usage. This workshop starts with a discussion on multi-com radios for multi-standard coexistence. It then focuses on advanced topics including software defined radio, DVB receivers, and MIMO wireless transceiver SoCs. Program schedule: 8:10 to 8:15am Introduction 8:15 to 9:25am Multi-Com Radios Stewart S Taylor, Intel 9:25 to 10:35am Multi-Mode RF Front-End Designs Noriharu Suematsu, Mitsubishi 10:35 to 10:50am Coffee break 10:50 to 12:00pm Multi-Band DS Frequency Synthesis John Rogers, Caleton University 12:00 to 1:30pm Lunch 1:30 to 2:40pm Software Defined Radio Asad Abidi, UCLA 2:40 to 2:55pm Coffee break 2:55 to 4:05pm Digital-Video-Broadcast Receivers Kunihiko Iizuka, Sharp 4:05 to 5:15pm MIMO Wireless Transceiver SoCs Masoud Zargari, Atheros 5:15pm-6:00pm Speaker Interview Session NanoTechnolgy:  NanoTechnolgy Magazine moved from Jan Mar/April  Summer Cost of printing lower in China Seeking permission from IEEE to print in China for cost Expect approval next week Contacts Dr. Wen Li – NanoMagazine Editor Dr. Meyya Meyyappan – Council President First Adcom meeting in Hong Kong August 2-5, coincident with Nano 2007 Bill Bidermann Ian Young http://www.ewh.ieee.org/tc/nanotech/

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